ammp-5024 30khz C 40 ghz traveling wave amplifer data sheet description avago technologies ammp-5024 is a broadband phemt gaas mmic twa designed for medium output power and high gain over the full 30 khz to 40 ghz frequency range. the design employs a 9-stage, cascade-connected fet structure to ensure fat gain and power as well as uniform group delay. e-beam lithography is used to produce uniform gate lengths of 0.15um and mbe technology assures precise semiconductor layer control. features ? surface mount package 5.0 x 5.0 x 2.0 mm ? wide frequency range 30khz C 40ghz ? high gain: 14.8 db typical @ 22ghz ? output p1db: 22 dbm typical @ 22ghz ? 50 ohm input and output match applications [1] ? broadband test and measurement applications pin function 1 v aux 2 not used 3 not used 4 rf out / vd 5 v g1 6 not used 7 v g2 8 rf in 1 2 3 7 5 6 4 8 rfin rfout/vd nc vaux nc nc vg2 vg1 attention: observe precautions for handling electrostatic sensitive devices. esd machine model (class a): 40v esd human body model (class 0): 150v refer to avago application note a004r: electrostatic discharge damage and control. note: msl rating = level 2a functional block diagram package diagram 1 2 3 7 5 6 4 8
2 electrical specifcations 1. all tested parameters guaranteed with measurement accuracy 0.5 db for gain. table 1. rf electrical characteristics (freq=22ghz, vd= 7.0v, idq=200ma, ta= 25c, zin=zo=50) parameter min typ. max unit small-signal gain, gain 12.5 14.8 16.5 db noise figure, nf 4.6 db output power at 1db gain compression, p1db 22 dbm third order intercept point; ?f=100mhz; pin=-5dbm, oip3 25 dbm input return loss, rlin 13 db output return loss, rlout 14 db reverse isolation, isolation 30 db table 2. rf electrical characteristics (freq=22ghz, vd= 4.0v, idq=160ma, ta= 25c, zin=zo=50) parameter min typ. max unit small-signal gain, gain 15 db noise figure, nf 4.6 db output power at 1db gain compression, p1db 19 dbm third order intercept point; ?f=100mhz; pin=-5dbm, oip3 18.5 dbm input return loss, rlin 13 db output return loss, rlout 14 db reverse isolation, isolation 27 db table 3. recommended operating range (vd=7v, vg2=open, ta= 25c, otherwise specifed) description specifcations unit comments min. typical max. drain supply voltage, vd 7 v total drain supply current, id 200 ma vg1 set for typical id first gate voltage, vg1 -3.5 -3.0 -2.5 v vd=7v, id=200ma saturated drain current, idss 350 ma vg1=0v first gate minimum drain current, idsmin (vg1) 80 ma vg1=-7v
3 table 4. thermal properties parameter test conditions value thermal resistance, jc jc = 16.2 c/w note: 1. channel-to-board thermal resistance is measured using qfi method. absolute minimum and maximum ratings table 5. minimum and maximum ratings description specifcations min. max. unit comments drain supply voltage, vd 10 v drain current, id 380 ma first gate voltage, vg1 -9.5 0 v first gate current, ig1 -38 1 ma second gate voltage, vg2 -3.5 4 v second gate current, ig2 -20 ma rf input power, pin 17 dbm cw channel temperature, tch +150 c storage temperature, tstg -65 +150 c maximum assembly temperature, tmax +260 c 20 second maximum notes: 1. operation in excess of any one of these conditions may result in permanent damage to this device. the absolute maximum ratings for dc and power parameters were determined at an ambient temperature of 25c unless noted otherwise.
4 selected performance plots these measurements are in 50 test environment at vd = 7v, id = 200ma, vg2 = open, ta = 25c. figure 1. gain and reverse isolation figure 2. return loss (input and output). frequency (ghz) isolation (db) 0 0 -20 -40 -60 -80 40 5 2 5 3 0 15 10 20 35 5 2 5 3 0 15 10 20 35 figure 3. output power (p1db and p3db) figure 4. output ip3 frequency (ghz) output power (dbm) 0 30 25 20 15 10 5 0 40 figure 5. npise figure frequency (ghz) 0 0 -5 -10 -15 -20 -25 -30 -35 -40 40 5 2 5 3 0 15 10 20 35 p1db p3db 5 2 5 3 0 15 10 20 35 frequency (ghz) nf (db) 0 10 8 6 4 2 0 40 0 10 20 30 40 50 0 5 10 15 20 25 30 35 40 frequency (ghz) oip3 (dbm) s21 s12 s11 s22 return loss (db) gain (db) 20 10 0 -10 -20
5 these measurements are in 50 test environment at vd = 4v, id = 160ma, vg2 = open, ta = 25c figure 6. gain and reverse isolation figure 7. return loss (input and output). frequency (ghz) gain (db) isolation (db) 0 20 10 0 -10 -20 0 -20 -40 -60 -80 40 5 2 5 3 0 15 10 20 35 5 2 5 3 0 15 10 20 35 s21 s12 figure 8. output power (p1db and p3db) figure 9. output ip3 frequency (ghz) output power (dbm) 0 30 25 20 15 10 5 0 40 figure 10. noise figure frequency (ghz) return loss (db) 0 0 -5 -10 -15 -20 -25 -30 -35 -40 40 5 2 5 3 0 15 10 20 35 s11 s22 p1db p3db 5 2 5 3 0 15 10 20 35 frequency (ghz) nf (db) 0 10 8 6 4 2 0 40 0 10 20 30 40 50 0 5 10 15 20 25 30 35 40 frequency (ghz) oip3 (dbm)
6 over temperature performance plots these measurements are in 50 test environment at vd = 7v, id = 200ma frequency (ghz) gain (db) 0 20 10 0 -10 -20 40 5 25 30 15 10 20 35 5 25 30 15 10 20 35 s21/25c s21/-40c s21/85c s11/25c s11/-40c s11/85c frequency (ghz) return loss (db) 0 0 -10 -20 -30 -40 40 frequency (ghz) isolation (db) 0 0 -20 -40 -60 -80 40 5 25 30 15 10 20 35 frequency (ghz) return loss (db) 0 0 -10 -20 -30 -40 40 5 25 30 15 10 20 35 5 25 30 15 10 20 35 frequency (ghz) nf (db) 0 10 8 6 4 2 0 40 frequency (ghz) p1db (dbm) 0 30 25 20 15 10 5 0 40 5 25 30 15 10 20 35 s12/25c s12/-40c s12/85c s22/25c s22/-40c s22/85c nf/25c nf/-40c nf/85c p1db/25c p1db/-40c p1db/85c figure 12. isolation and temperature. figure 11. gain and temperature. figure 13. input return loss and temperature. figure 14. output return loss and temperature. figure 15. noise figure and temperature. figure 16. p1db and temperature.
7 biasing and operation ammp-5024 is biased with a single positive drain supply (vd) a negative gate supply (vg1) and has a positive control gate supply (vg2). for best overall performance the recommended bias condition for the ammp-5024 is vd =7v and id = 200 ma. to achieve this drain current level, vg1 is typically between C2.5 to C3.5v. typically, dc current fow for vg1 is C10 ma. open circuit is the default setting for vg2 when not utilizing gain control. using the simplest form of assembly, the device is capable of delivering fat gain over a 2C40 ghz range. however, this device is designed with dc coupled rf i/o ports, and operation may be extended to lower frequencies (<2 ghz) through the use of of-chip low- frequency extension circuitry and proper external biasing components. with low frequency bias extension it may be used in a variety of time domain applications (through 40 gb/s). when bypass capacitors are connected to the aux pads, the low frequency limit is extended down to the corner frequency determined by the bypass capacitor and the combination of the on-chip 50 ohm load and small de-queing resistor. at this frequency the small signal gain will increase in magnitude and stay at this elevated level down to the point where the caux bypass typical scattering parameters please refer to for typical scattering parameters data. capacitor acts as an open circuit, efectively rolling of the gain completely. the low frequency limit can be approximated from the following equation: 1 f caux = 2 p caux (ro + r deq ) where: ro is the 50 gate or drain line termination resistor. rdeq is the small series dequeing resistor and 10. caux is the capacitance of the bypass capacitor connected to the aux drain and aux gate pad in farads. with the external bypass capacitors connected to the aux gate and aux drain pads, gain will show a slight increase between 1.0 and 1.5 ghz. this is due to a series combination of caux and the on-chip resistance but is exaggerated by the parasitic inductance (lc) of the bypass capacitor and the inductance of the bond wire (ld). input and output rf ports are dc coupled; therefore, dc decoupling capacitors are required if there are dc paths. (do not attempt to apply bias to these pads.)
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2013 avago technologies. all rights reserved. av02-0465en - july 8, 2013 ordering information part number devices per container container ammp-5024-blkg 10 antistatic bag ammp-5024-tr1g 100 7 reel ammp-5024-tr2g 500 7 reel package dimension, pcb layout and tape and reel information please refer to avago technologies application note 5520, amxp-xxxx production assembly process (land pattern a)
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